1. Field of Invention
The present invention relates to a method to fabricate strain-relaxed SiGe layers, and more particularly to a method to fabricate a patterned strain-relaxed SiGe epitaxy with threading dislocation density control.
2. Related Art
The semiconductor and integrated circuit technology has been developed to be compact with high operation speed in recent years. How to increase the operation speed of the semiconductor device and lower power consumption constitutes an important issue in the very large scale integration (VLSI) field.
Researches on SiGe material have shown that deposition of a strained Si after depositing a strain-relaxed SiGe layer on a silicon substrate, increases electron shift mobility in a channel of the semiconductor device and, consequently, the semiconductor device performance.
U.S. Pat. No. 6,515,335 discloses a Ge wetting layer formed on a silicon-on-insulator (SOI). A SiGe island-shaped layer is then formed on the Ge wetting layer. A planarized SiGe layer is formed to cover the SiGe island-shaped layer. After a thermal treatment is performed, diffusion occurs among the silicon layer on the SOI, the SiGe island-shaped layer and the planarized SiGe layer, to form a uniform low-strain SiGe layer on the oxide layer. The threading dislocation occurs on the SiGe layer close to the oxide layer, so there is no cell dislocation on the topmost SiGe layer.
U.S. Pat. No. 6,291,321 discloses a process of forming gradual Ge layers at different temperatures. Cell dislocation at interfaces between the layers increases, due to the roughness of the interfaces. In the disclosure of this patent, the roughness of the interfaces is reduced by performing a chemical mechanical polishing process in patent 321, which results in a reduction of cell dislocation. However, the occurrence location of the dislocation cannot be control.
Current technology trends now are focusing on the formation of gradual Ge layers with low threading dislocation where dislocation is well controlled. A main SiGe layer is formed on the gradual Ge layer. Therefore, this structure doesn't have defects caused by large strain variation of lattices. Thereby, relaxation of lattices increases. This structure is applied in a strained Si/Sige CMOS manufacture process.
However, the manufacture process still leads to high threading dislocation density and is not good for ICs manufacturing. Large current leakage and low carrier shift mobility occurs to threading dislocation.
In view of the current need for semiconductor devices, a higher Ge content leads to faster speed and better performance. However, high threading dislocation density because of the thickness of the epitaxial layer occurs. For the foregoing reasons, there is a need for SiGe epitaxial layers with low threading dislocation density.